A Novel Architecture for Queue Management in the ATM Network

Due to the natural randomness of broadband traffic, queues are required at various places in the asynchronous transfer mode (ATM) network to absorb instantaneous traffic bursts that may temporarily exceed the network bandwidth. A queue management algorithm will manage the queued cells in such a way that higher priority cells will always be served first, low priority cells will be discarded when the queue is full, and for same-priority cells any interference between them will be prevented. This paper presents four architecture designs for such queue management and compares their implementation feasibility and hardware complexity. This paper introduces the concept of assigning a departure sequence number to every cell in the queue so that the effect of long-burst traffic to other cells is avoided. A novel architecture to implement the queue management is proposed. The architecture applies the concepts of fully distributed and highly parallel processing to schedule cells’ sending or discarding sequence. To support the architecture, a VLSI chip (called Sequencer), which contains about 150K CMOS transistors, has been designed in a regular structure such that the queue size and the number of priority levels can grow flexibly.